1. Technical Field
The present disclosure relates to a clock rate controller, in particular, to a clock controller for regulating a clock rate of an internal device (i.e. for controlling the speed which the internal device processes the packet) in an electronic device to adjust a usage of the first-input-first-output (FIFO) buffer, and a method and an electronic device thereof, wherein the usage is the number of the registers of the FIFO buffer in which the packets have been stored.
2. Description of Related Art
With the technology development, the new electronic device products are provided in the market frequently, and the high speed transmission interfaces of different kinds are specified and proposed minutely. However, the clock rate associated with the internal device of the current electronic device cannot keep up with the data transmission speed of the host (p.s. the host can be the hub or the computer according to the different condition), and thus a clock rate controller and the FIFO buffer are disposed in the electronic device.
The current clock rate controller can track the packet transmission speed of the host, and since the FIFO buffer can buffer the packets meanwhile, the internal device has a regulation time to control the phase lock loop (PLL) thereof based upon the control signal of the clock rate controller, such that the clock rate that the internal device processes the packet stored in the FIFO buffer is adjusted. Generally speaking, the data transmission speed of the computer is more stable. Once the clock rate of the internal device keeps up with the packet transmission speed of the computer, the usage of the FIFO buffer maintains a specific level.
Troublesomely, the number of the ports providing the electronic device to connect with the computer is limited, and thus there is a hub connected between the computer and the electronic device. Taking the universal serial bus (USB) hub for example, if the USB hub is not designed well, it causes the start of frame (SOF) which is transmitted to the electronic device from the hub cannot meet the specification of one SOF per microsecond and the normal standard of 500 nanosecond tolerance.
When the transmission speed of the SOF is too high (i.e. the packet transmission speed of the hub is too high), and the FIFO buffer does not have enough storage space and the well-designed processing mechanism, it causes the overflow of the FIFO buffer, such that some packets are discarded. The electronic device can be the USB speaker for example, and since some audio packets are discarded, it causes the sound glitch and the poor audio quality.
In addition, the conventional electronic device can make the clock rate of the internal device keep up with the packet transmission speed of the host to adjust the usage of the FIFO buffer by controlling the PLL, but after the clock rate of the internal device keeps up with the packet transmission speed of the host, the conventional electronic device does not pull the usage of the FIFO buffer back to a specific interval. Thus, the usage of the FIFO buffer of the conventional electronic device may maintain a level near the overflow edge. Meanwhile, if the packet transmission speed of the host is increased, there is not enough for the internal device to process the packet stored in the FIFO buffer. Accordingly, the FIFO buffer overflows, and some packets are discarded.